TSN Endpoint
A low-footprint, highly configurable, 100% hardware only IEEE 802.1 Time Sensitive Networking (TSN) End Node solution, specifically designed for synchronous, deterministic, real-time and high-availability distributed systems. Allows running synchronization, scheduling, filtering, preemption, etc. completely independent and standalone from the user application and can be connected to any MAC.
| Article | Description | Price |
|---|---|---|
| TSN-END-NODE-EVAL | Bitstream for T*Square Ti60-256 Education Board (including tools and base configuration, limited to 1 hour of runtime from reset). | 0,- € |
| TSN-END-NODE-PRJ | TSN End Node and Adjustable Counter Clock IP Core as Project License: Unencrypted VHDL source code, including testbench and simulation framework. Reference design for the T*Square Ti60-256 Education Board as source code. Project license, no quantity limitation. Maintenance and support for the IP cores included for the first year, integration support not included. |
22300,- € |
| TSN-END-NODE-SITE | TSN End Node and Adjustable Counter Clock IP Core as Site License: Unencrypted VHDL source code, including testbench and simulation framework. Reference design for the T*Square Ti60-256 Education Board as source code. Site license, no quantity limitation. Maintenance and support for the IP cores included for the first year, integration support not included. |
40200,- € |
Key Features
- Up to 8 different priority queues, with freely definable VLAN priorities
- Up to 64 phases per cycle according to priority queues
- Cycle time and phase durations freely configurable (max 1 ms, min 15.625 us)
- Cut-Through (<2us delay @ 1G) or Strore-And-Forward frame forwarding
- Frame scheduling according to IEEE 802.1 Qbv
- Cyclic forwarding according to IEEE 802.1 Qch
- Credit based shaper according to IEEE 802.1 Qav
- Frame preemption according to IEEE 802.1 Qbu and IEEE 802.3 br can be enabled for the lowest priority to allow maximum bandwidth usage
- Registerset to configure according to IEEE 802.1 Qcc
- Synchronization with sub-microsecond accuracy according to IEEE 1588 Default-, Utility- or Power-Profile or according to IEEE 802.1 AS
- Supports up to 8 AXI streaming interfaces, one for each priority/phase
- Full line speed
- AXI4 Light register set or static configuration
- MII/RMII/GMII/RGMII Interface support
- Optional frame and error counters
SPI-Master/Slave IP
The SPI slave IP core can be used in an HDL description to establish communication with an SPI master (the common case is a microcontroller).
The SPI Slave IP Core offers high flexibility to enable usage in a broad spectrume of applications.
There is also SPI-Master-IP-Core available.
| Article | Description | Price |
|---|---|---|
| SPI-MASTER-EVAL | Bitstream for T*Square T20-100/144 Education Board | 0,- € |
| SPI-SLAVE-EVAL | Bitstream for T*Square T20-100/144 Education Board | 0,- € |
| SPI-MASTER-RTL | SPI-Master: unencrypted source code, including simulation model and simulation environment. No quantity restriction. Includes 8 hours of support and a 10% discount code for the next 40 hours of support. | 8900,- € |
| SPI-SLAVE-RTL | SPI-Slave: unencrypted source code, including simulation model and simulation environment. No quantity restriction. Includes 8 hours of support and a 5% discount code for the next 40 hours of support. | 3900,- € |
Functional overview of the SPI slave IP core.
Key Features
- Configurable SPI clock phase and polarity
- Advanced synchronization scheme enables SPI clock frequency up to 1.66×system clock frequency: SPI clock rate can be higher than FPGA system clock rate
- Streaming interfaces to logic
- Optional CRC16 or CRC32 calculation
- Automated SPI frame/packed enumeration
- Fully synthesizable design
- Supports Intel/Altera Avalon and AXI streaming interfaces
Applications
- Resource efficient connection of FPGA to a microcontroller or SoC
- Allows even for low cost FPGA at high SPI data rates
- Coupling of FPGA to FPGA
FPGA Lock IP
Prevent Overbuilding and secure your design with the FPGA Lock IP
The FPGA Lock is a small FPGA IP core that prevents overbuilding and cloning of your FPGA-based systems and consequently protects your revenue. It can also be used to guarantee hardware integrity in Safety Critical, Medical or Military/Defence applications.
The IP core uses less than 1 kLUT FPGA resources, one user IO and hardly any PCB realestate. It is intended to communicate with Microchip‘s ATSHA204A hardened crypto authenti- cation IC. Users can prevent IP theft and Overbuilding.
The FPGA Lock IP uses symmetric cryptography, meaning the FPGA Lock IP and the crypto chip share a common secret key.
Free Evaluation with T*Square Educations Boards in combination with the FPGA-Lock-PMOD Dongle!
| Article | Description | Price |
|---|---|---|
| FPGA-LOCK-EVAL | Encrypted source files. The secret key is used for evaluation only. The IP can be evaluated with the T*Square T20-100/144 Education Board in combination with the FPGA-Lock-PMOD Dongle. | 0,- € |
| FPGA-LOCK-FIX | Encrypted source files. The secret key is used for production only. No MOQ for crypto chip. | 1.000,- € |
| FPGA-LOCK-CUST | Encrypted source files. The customer specific secret key is used for just one customer, but it is unknown to this customer. MOQ for crypto chip. | 2.000,- € |
| FPGA-LOCK-RTL | RTL source files. Customer has full control over the secret key. | 7.500,- € |
- Test triggered, core Reads device ID.
- Core sends 256 bit random challenge.
- ATSHA204a perfoms SHA256 hash on the challenge, its ID and a programmed 256 bit secret key. The hash result is returned to the core.
- The core also performs the hash on the challenge, device ID and secret key (that it knows).
- If the two sets of hash results match then a device with the correctly programmed secret key is present, FPGA functionality is enabled