A low-footprint, highly configurable, 100% hardware only IEEE 802.1 Time Sensitive Networking (TSN) End Node solution, specifically designed for synchronous, deterministic, real-time and high-availability distributed systems. Allows running synchronization, scheduling, filtering, preemption, etc. completely independent and standalone from the user application and can be connected to any MAC.

Key Features

• Up to 8 different priority queues, with freely definable VLAN priorities
• Up to 64 phases per cycle according to priority queues
• Cycle time and phase durations freely configurable (max 1 ms, min 15.625 us)
• Cut-Through (<2us delay @ 1G) or Strore-And-Forward frame forwarding
• Frame scheduling according to IEEE 802.1 Qbv
• Cyclic forwarding according to IEEE 802.1 Qch
• Credit based shaper according to IEEE 802.1 Qav
• Frame preemption according to IEEE 802.1 Qbu and IEEE 802.3 br can be enabled for the lowest priority to allow maximum bandwidth usage
• Registerset to configure according to IEEE 802.1 Qcc
• Synchronization with sub-microsecond accuracy according to IEEE 1588 Default-, Utility- or Power-Profile or according to IEEE 802.1 AS
• Supports up to 8 AXI streaming interfaces, one for each priority/phase
• Full line speed
• AXI4 Light register set or static configuration
• MII/RMII/GMII/RGMII Interface support
• Optional frame and error counters

The SPI slave IP core can be used in an HDL description to establish communication with an SPI master (the common case is a microcontroller).

The SPI Slave IP Core offers high flexibility to enable usage in a broad spectrume of applications.
There is also SPI-Master-IP-Core available.

Functional overview of the SPI slave IP core.

Key Features

• Configurable SPI clock phase and polarity
• Advanced synchronization scheme enables SPI clock frequency up to 1.66×system clock frequency: SPI clock rate can be higher than FPGA system clock rate
• Streaming interfaces to logic
• Optional CRC16 or CRC32 calculation
• Automated SPI frame/packed enumeration
• Fully synthesizable design
• Supports Intel/Altera Avalon and AXI streaming interfaces

Applications

• Resource efficient connection of FPGA to a microcontroller or SoC
• Allows even for low cost FPGA at high SPI data rates
• Coupling of FPGA to FPGA

The Aurora protocol defined by AMD (formerly Xilinx) is a lightweight, high speed communication protocol for efficient inter-FPGA communication. The advantage of Aurora is low protocol overhead, high throughput, efficient resource utilisation and ease of implementation.
The Aurora 64b66b interface provided by NSD Ltd provides an easy to integrate production-ready solution for Efinix devices that can be used for inter-Efinix device communication or for operation with AMD devices or any other device using the Aurora protocol.
The current IP supports single lane communication with no flow control. Further functionality is being added.

The FPGA Lock is a small FPGA IP core that prevents overbuilding and cloning of your FPGA-based systems and consequently protects your revenue. It can also be used to guarantee hardware integrity in Safety Critical, Medical or Military/Defence applications.
The IP core uses less than 1 kLUT FPGA resources, one user IO and hardly any PCB realestate. It is intended to communicate with Microchip‘s ATSHA204A hardened crypto authenti- cation IC. Users can prevent IP theft and Overbuilding.
The FPGA Lock IP uses symmetric cryptography, meaning the FPGA Lock IP and the crypto chip share a common secret key.

Free Evaluation with T*Square Educations Boards in combination with the FPGA-Lock-PMOD Dongle!