The Video Daughter-Card can be used to interface with one DVI Source and one DVI Sink. Additionally, it is HDMI-Ready for a real HDMI IP in the FPGA. With the use of Efinix HSIOs up to 1500 Mbps are supported per lane which results in resolutions up to 1920x1080 @ 60 Hz. In combination with a framebuffer e.g. in Hyper-Ram various applications can be served. Because the Interface to the FPGA is based on fast LVDS, only 4 differential IOs + I2C and HPD are needed for sink or source. Texas Instruments TMDS141 guarantees a true TMDS signal for both sink and source. Through I2C the video sinks EDID can be read, and an EDID in the FPGA can be generated for source applications as well