» Description
The Ti60 FPGA features the high-density, low-power 16 nm Efinix® Quantum® fabric wrapped with an I/O interface in a small footprint package for easy integration. Ti60 FPGAs support mobile, edge, AI IoT, and sensor fusion markets that need low power, a small footprint, and a multitude of I/Os. Ti60 FPGAs:
» Features
- Are fabricated on a 16 nm process.
- Have high-voltage I/O (HVIO)—Simple I/O blocks that support the single-ended LVTTL and LVCMOS I/O standards.
- Have high-speed I/O (HSIO)—Complex I/O blocks that support single-ended and differential I/O, LVDS, subLVDS, Mini-LVDS, and RSDS (RX, TX, and bidirectional) up to 1.6 Gbps, and also operate as MIPI lanes at 1.5 Gbps.
- Have device configuration options including a standard SPI and JTAG interfaces.
- Are fully supported by the Efinity® software, an RTL-to-bitstream compiler.
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Ti60F100S3F2I3
Ti60F256I4
Tech. Specifications
| Logic Elements: | 62016 |
| RAM: | 2.62 Mb |
| RAM blocks (10Kb): | 256 |
| DSP Blocks: | 160 |
| Temperature range: | - 40° - 100° C |
VPE/Packaging Unit: 5 pcs.
Standard lead time: 10 weeks
