The Ti180 FPGA features the high-density, low-power 16 nm Efinix^® Quantum^® fabric wrapped with an I/O interface in a small footprint package for easy integration. Ti180 FPGAs support mobile, edge, AI IoT, and sensor fusion markets that need low power, a small footprint, and a multitude of I/Os. Ti180 FPGAs:

• Are fabricated on a 16 nm process.
• Have high-voltage I/O (HVIO)—Simple I/O blocks that support the single-ended LVTTL and LVCMOS I/O standards.
• Have high-speed I/O (HSIO)—Complex I/O blocks that support single-ended and differential I/O, LVDS, subLVDS, Mini-LVDS, and RSDS (RX, TX, and bidirectional) up to 1.6 Gbps, and also operate as MIPI lanes at 1.5 Gbps.
• MIPI D-PHY hard IP with speeds up to 2.5 Gbps
• LPDDR4/LPDDR4x PHY (supporting x16 or x32 DQ widths) with memory controller hard IP
• Have device configuration options including a standard SPI and JTAG interfaces.
• Are fully supported by the Efinity^® software, an RTL-to-bitstream compiler.