TSN Endpoint
A low-footprint, highly configurable, 100% hardware only IEEE 802.1 Time Sensitive Networking (TSN) End Node solution, specifically designed for synchronous, deterministic, real-time and high-availability distributed systems. Allows running synchronization, scheduling, filtering, preemption, etc. completely independent and standalone from the user application and can be connected to any MAC.
| Article | Description | Price |
|---|---|---|
| TSN-END-NODE-EVAL | Bitstream for T*Square Ti60-256 Education Board (including tools and base configuration, limited to 1 hour of runtime from reset). | 0,- € |
| TSN-END-NODE-PRJ | TSN End Node and Adjustable Counter Clock IP Core as Project License: Unencrypted VHDL source code, including testbench and simulation framework. Reference design for the T*Square Ti60-256 Education Board as source code. Project license, no quantity limitation. Maintenance and support for the IP cores included for the first year, integration support not included. |
22300,- € |
| TSN-END-NODE-SITE | TSN End Node and Adjustable Counter Clock IP Core as Site License: Unencrypted VHDL source code, including testbench and simulation framework. Reference design for the T*Square Ti60-256 Education Board as source code. Site license, no quantity limitation. Maintenance and support for the IP cores included for the first year, integration support not included. |
40200,- € |
Key Features
- Up to 8 different priority queues, with freely definable VLAN priorities
- Up to 64 phases per cycle according to priority queues
- Cycle time and phase durations freely configurable (max 1 ms, min 15.625 us)
- Cut-Through (<2us delay @ 1G) or Strore-And-Forward frame forwarding
- Frame scheduling according to IEEE 802.1 Qbv
- Cyclic forwarding according to IEEE 802.1 Qch
- Credit based shaper according to IEEE 802.1 Qav
- Frame preemption according to IEEE 802.1 Qbu and IEEE 802.3 br can be enabled for the lowest priority to allow maximum bandwidth usage
- Registerset to configure according to IEEE 802.1 Qcc
- Synchronization with sub-microsecond accuracy according to IEEE 1588 Default-, Utility- or Power-Profile or according to IEEE 802.1 AS
- Supports up to 8 AXI streaming interfaces, one for each priority/phase
- Full line speed
- AXI4 Light register set or static configuration
- MII/RMII/GMII/RGMII Interface support
- Optional frame and error counters